Marantz DV7600 Manuel de service télécharger pdf (Page 32)

CMPCLK, FSCLKN2 — PCM Audio Input Bit Clock

Digital-audio bit clock input. FSCLKN2 operates asynchronously from all other DSP AB clocks.

The active edge of FSCLKN2 can be programmed by the DSP.

CMPDAT, FSDATAN2 — PCM Audio Data Input Number Two

Digital-audio data input that can accept either one compressed line or 2 channels of PCM

data. FSDATAN2 can be sampled with either edge of FSCLKN2, depending on how FSCLKN2

has been configured.

FDBCK — Reserved

This pin is reserved and should be pulled up with an external 10k resistor.

FDBDA — Reserved

This pin is reserved and should be pulled up with an external 10k resistor.

PLLVDD — PLL Supply Voltage

2.5 V PLL supply.

PLLVSS — PLL Ground Voltage

PLL ground.

RESET

— Master Reset Input

Asynchronous active-low master reset input. Reset should be low at power-up to initialize the

DSP and to guarantee that the device is not active during initial power-on stabilization periods.

At the rising edge of reset the host interface mode of DSP AB is selected contingent on the

state of the FHS0, FHS1, and FHS2 pins. At the rising edge of reset the host interface mode

of DSP C is selected contingent on the state of the UHSO, UHS1, and UHS2 pins. If reset is

low all bidirectional pins are high-Z inputs.

TEST — Reserved

This should be tied low for normal operation.

MCLK — Audio Master Clock

Bidirectional master audio clock. As an output, MCLK provides a low jitter oversampling clock.

MCLK supports all standard oversampling frequencies.

SCLK0 — Audio Output Bit Clock

Bidirectional digital-audio output bit clock for AUDATA0, AUDATA1, AUDATA2, and AUDATA3.

As an output, SCLK0 can provide 32 Fs, 64 Fs, 128 Fs, 256 Fs, or 512 Fs frequencies and is

synchronous to MCLK. As an input, SCLK0 is independent of MCLK.

SCLK1 — Audio Output Bit Clock

Bidirectional digital-audio output bit clock for AUDATA4, AUDATA5, AUDATA6, and AUDATA7.

As an output, SCLK1 can provide 32 Fs, 64 Fs, 128 Fs, 256 Fs, or 512 Fs frequencies and is

synchronous to MCLK. As an input, SCLK1 is independent of MCLK.

LRCLK0 — Audio Output Sample Rate Clock

Bidirectional digital-audio output frame clock for AUDATA0, AUDATA1, AUDATA2, and

AUDATA3. As an output, LRCLK0 can provide all standard output sample rates up to 192 kHz

and is synchronous to MCLK. As an input, LRCLK0 is independent of MCLK.

LRCLK1 — Audio Output Sample Rate Clock

Bidirectional digital-audio output frame clock for AUDATA4, AUDATA5, AUDATA6, and

AUDATA7. As an output, LRCLK1 can provide all standard output sample rates up to 192 kHz

and is synchronous to MCLK. As an input, LRCLK1 is independent of MCLK.

AUDATA0 — Digital Audio Output 0

PCM digital-audio data output.

AUDATA1 — Digital Audio Output 1

PCM digital-audio data output.

AUDATA2 — Digital Audio Output 2

PCM digital-audio data output.

AUDATA3, XMT958A — Digital Audio Output 3, S/PDIF Transmitter

CMOS level output that outputs a biphase-mark encoded (S/PDIF) IEC60958 signal or digital

audio data which is capable of carrying two channels of PCM digital audio.

AUDATA4, GPIO28 — Digital Audio Output 4, General Purpose I/O

PCM digital-audio data output. This pin can act as a general-purpose input or output that can

be individually configured and controlled by DSP C.

AUDATA5, GPIO29 — Digital Audio Output 5, General Purpose I/O

PCM digital-audio data output. This pin can act as a general-purpose input or output that can

be individually configured and controlled by DSP C.

AUDATA6, GPIO30 — Digital Audio Output 6, General Purpose I/O

PCM digital-audio data output. This pin can act as a general-purpose input or output that can

be individually configured and controlled by DSP C.

AUDATA7, XMT958B, GPIO31 — Digital Audio Output 7, S/PDIF Transmitter, General Purpose I/O

CMOS level output that contains a biphase-mark encoded (S/PDIF) IEC60958 signal or digital

audio data which is capable of carrying two channels of PCM digital audio. This pin can also

act as a general-purpose input or output that can be individually configured and controlled by

DSP C.

DBCK — Debug Clock

Must be tied high to 10k ohm resistor.

DBDA — Debug Data

Must be tied high to 10k ohm resistor.

SLCKN, GPIO22 — PCM Audio Input Bit Clock, General Purpose I/O

Digital-audio bit clock that is an input. SCLKN operates asynchronously from all other DSP AB

clocks. The active edge of SCLKN can be programmed by the DSP. This pin can act as a

general-purpose input or output that can be individually configured and controlled by DSP C.

LRCLKN, GPIO23 — PCM Audio Input Sample Rate Clock, General Purpose I/O

Digital-audio frame clock input. LRCLKN operates asynchronously from all other DSP AB

clocks. The polarity of LRCLKN for a particular subframe can be programmed by the DSP.

This pin can act as a general-purpose input or output that can be individually configured and

controlled by DSP C.

SDATAN0, GPIO24 — PCM Audio Input Data, General Purpose I/O

Digital-audio PCM data input. This pin can act as a general-purpose input or output that can

be individually configured and controlled by DSP C.

SDATAN1, GPIO25 — PCM Audio Input Data, General Purpose I/O

Digital-audio PCM data input. This pin can act as a general-purpose input or output that can

be individually configured and controlled by DSP C.

SDATAN2, GPIO26 — PCM Audio Input Data, General Purpose I/O

Digital-audio PCM data input. This pin can act as a general-purpose input or output that can

be individually configured and controlled by DSP C.

SDATAN3, GPIO27 — PCM Audio Input Data, General Purpose I/O

Digital-audio PCM data input. This pin can act as a general-purpose input or output that can

be individually configured and controlled by DSP C.

SCS

— Host Serial SPI Chip Select

SPI mode active-low chip-select input signal.

SCCLK — Serial Control Port Clock

This pin serves in serial host mode as one of two address input pins used to select one of four

parallel registers. It serves as the serial open-drain SPI clock input or the I

clock input.

SCDIN — SPI Serial Control Data Input

In SPI mode this pin serves as the data input pin.

SCDOUT, SCDIO — Serial Control Port Data Input and Output

In I

mode, this pin serves as the open-drain bidirectional data pin. In SPI mode this pin

serves as the data output pin.

INTREQ

— Control Port Interrupt Request

Open-drain interrupt-request output. This pin is driven low to indicate that DSP C has outgoing

control data and should be serviced by the host.

HDATA7, GPIO7 — DSP C Bidirectional Data Bus, General Purpose I/O

HDATA6, GPIO6

HDATA5, GPIO5

HDATA4, GPIO4

HDATA3, GPIO3

HDATA2, GPIO2

HDATA1, GPIO1

HDATA0, GPIO0

In parallel host mode, these pins provide a bidirectional data bus. These pins can also act as

general purpose input or output pins that can be individually configured and controlled by DSP

A0, GPIO13

— Host Parallel Address Bit 0, General Purpose I/O

In parallel host mode, this pin serves as the LS Bit of a two bit address input used to select

one of four parallel registers. This pin can act as a general-purpose input or output that can be

individually configured and controlled by DSP C.

A1, GPIO12 — Host Address Bit 1, General Purpose I/O

In parallel host mode, this pin serves as the MS Bit of a two bit address input used to select

one of four parallel registers. This pin can act as a general-purpose input or output that can be

individually configured and controlled by DSP C.

, R/W, GPIO11 — Host Parallel Output Enable, Host Parallel R/W, General Purpose I/O

In Intel parallel host mode, this pin serves as the active-low data bus enable input. In Motorola

parallel host mode, this pin serves as the read-high/write-low control input signal. This pin can

act as a general-purpose input or output that can be individually configured and controlled by

DSP C.

IC11 : CS494003 (DSP)

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Marantz DV7600 Manuel de service Page 32

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